PD70F3826_15 Datasheet, PDF (60/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 22. INTERRUPT/EXCEPTION PROCESSING FUNCTION
Table 22-1. Interrupt Source List (2/3
Type
Classification Default
Priority
Name
Trigger
Generating
Unit
Interrupt
Control
Register
JE3E JF3E JG3E
Maskable Interrupt
41 INTTAA0OV TAA0 overflow
TAA0
TAA0OVIC √
√
√
42 INTTAA0CC0 TAA0 capture 0/compare 0 match
TAA0
TAA0CCIC0 √ √ √
43 INTTAA0CC1 TAA0 capture 1/compare 1 match
TAA0
TAA0CCIC1 √ √ √
44 INTTAA1OV TAA1 overflow
TAA1
TAA1OVIC √ √ √
45 INTTAA1CC0 TAA1 capture 0/compare 0 match
TAA1
TAA1CCIC0 √ √ √
46 INTTAA1CC1 TAA1 capture 1/compare 1 match
TAA1
TAA1CCIC1 √ √ √
47 INTTAA2OV TAA2 overflow
TAA2
TAA2OVIC √ √ √
48 INTTAA2CC0 TAA2 capture 0/compare 0 match
TAA2
TAA2CCIC0 √ √ √
49 INTTAA2CC1 TAA2 capture 1/compare 1 match
TAA2
TAA2CCIC1 √ √ √
50 INTTAA3OV TAA3 overflow
TAA3
TAA3OVIC √ √ √
51 INTTAA3CC0 TAA3 capture 0/compare 0 match
TAA3
TAA3CCIC0 √ √ √
52 INTTAA3CC1 TAA3 capture 1/compare 1 match
TAA3
TAA3CCIC1 √ √ √
53 INTTAA4OV TAA4 overflow
TAA4
TAA4OVIC √ √ √
54 INTTAA4CC0 TAA4 capture 0/compare 0 match
TAA4
TAA4CCIC0 √ √ √
55 INTTAA4CC1 TAA4 capture 1/compare 1 match
TAA4
TAA4CCIC1 √ √ √
59 INTTM0EQ0 TMM0 compare match
TMM0
TM0EQIC0 √ √ √
60 INTTM1EQ0 TMM1 compare match
TMM1
TM1EQIC0 √ √ √
61 INTTM2EQ0 TMM2 compare match
TMM2
TM2EQIC0 √ √ √
62 INTTM3EQ0 TMM3 compare match
TMM3
TM3EQIC0 √ √ √
67 INTCF0R
/INTUC3R
/INTIIC1
CSIF0 transfer completion/UARTC3 reception
completion/UARTC3 reception error/IIC1 transfer
completion
CSIF0
CE0RIC
√√√
/UARTC3 /UC3RIC
/IIC1
/IICIC1
68 INTCF0T
/INTUC3T
CSIF0 continuous transfer write enable/ UARTC3
continuous transfer write enable
CSIF0
CF0TIC
√√√
/UARTC3 /UC3TIC
69 INTCF1R
/INTUC1R
/INTIIC0
CSIF1 reception completion/ CSIF1 reception error
/UARTC1 reception completion/UARTC1 reception
error/IIC0 transfer completion
CSIF1
CF1RIC
−−√
/UARTC1 /UC1RIC
/IIC0
/IICIC0
70 INTCF1T
/INTUC1T
CSIF1 continuous transfer write enable/ UARTC1
continuous transfer write enable
CSIF1
CF1TIC
−−√
/UARTC1 /UC1TIC
71 INTCF2R
CSIF2 reception completion/CSIF2 reception error/
CSIF2
CF2RIC
√√√
/INTUC0R UARTC0 reception completion/UARTC0 reception error /UARTC0 /UC0RIC
72 INTCF2T
/INTUC0T
CSIF2 continuous transfer write enable/UARTC0
continuous transfer write enable
CSIF2
CF2TIC
√√√
/UARTC0 /UC0TIC
73 INTCF3R
CSIF3 reception completion/CSIF3 reception error
CSIF3
CF3RIC
−√√
74 INTCF3T
CSIF3 continuous transfer write enable
CSIF3
CF3TIC
−√√
78 INTCF4R
CSIF4 reception completion/CSIF4 reception error
CSIF4
CF4RIC
−√√
79 INTCF4T
CSIF4 continuous transfer write enable
CSIF4
CF4TIC
−√√
87 INTUC2R
/INTIIC2
UARTC2 reception completion/UARTC2 reception UARTC2 UC2RIC
error/IIC2 transfer completion
/IIC2
/IICIC2
√√√
88 INTUC2T
UARTC2 continuous transfer write enable
UARTC2 UC2TIC
√√√
90 INTAD
A/D converter completion
A/D
ADIC
√√√
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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