PD70F3826_15 Datasheet, PDF (57/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 21. DMA CONTROLLER
The following figure shows the configuration of DMA controller.
CPU
Internal RAM
On-chip
peripheral I/O
Internal bus
On-chip peripheral I/O bus
Data
control
Address
control
Count
control
Channel
control
DMA source address
register n (DSAnH/DSAnL)
DMA destination address
register n (DDAnH/DDAnL)
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
Remark n = 0 to 3
DMAC
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 57 of 75