PD70F3826_15 Datasheet, PDF (55/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 20. ETHERNET CONTROLLER
20. ETHERNET CONTROLLER
In the V850ES/Jx3-E, one channel of Ethernet controller is provided.
{ 10 Mbps/100 Mbps MAC function conforming to the IEEE802.3 standard
• Full-duplex and half-duplex communications and a flow control function are supported
• On-chip packet filtering function based on address type
• On-chip VLAN detection function
{ Ethernet-dedicated DMA controller
• Reception status DMA transfer possible
• Reading (in pointer-chain format), analysis, and writing back of buffer descriptors possible
• Interrupt control functions for packet transfers
{ FIFO controller
• Transmission/reception FIFO size: Transmission FIFO (2 KB), reception FIFO (2 KB)
• On-chip FIFO status register
• Interrupts occur in accordance with the transmission/reception status and FIFO status.
{ MII is supported as the interface with physical-layer devices (PHY)
{ On-chip reception checksum calculation function conforming to RFC1071
The following figure shows the configuration of USB function controller.
V850ES/Jx3-E
Internal
bus interface
DMA
controller
FIFO
controller
Transmission
FIFO
(2 KB)
Reception
FIFO
(2 KB)
Ethernet
MAC
MII/RMII
I/O
buffer
PHY
TPO+
TPO-
TPI+
TPI-
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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