PD70F3826_15 Datasheet, PDF (31/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 5. CLOCK GENERATION FUNCTION
The following figure shows the configuration of the clock generation function.
FRC bit
XT1
Subclock ^fXT
XT2
oscillator
Prescaler 3
fXT RTC clock,
WDT clock
RTC clock
MFRC
bit
PLLON
bit
X1
Main clock
fX
PLL
X2
oscillator
IDLE
control
IDLE mode
IDLE ^fXX
control
Prescaler 2
CK2-CK0
bit
CK3 bit
Main clock
oscillator
stop control
STOP mode
SELPLL
bit
fXX/32
fXX/16
fXX/8
fXX/4
fXX/2
fXX
HALT
mode
HALT ^fCPU
control
fCLK
CPU clock
Internal
system clock
EXCLK^Note
UCKSEL
bit
Internal
fR
oscillator
RSTOP bit
Prescaler 1
1/8 divider
WDT clock,
timer M clock
Peripheral clock
(include Ethernet)
USB clock
Note
Remark
V850ES/JG3-E only
fX: Main clock oscillation frequency
fR: Internal oscillation frequency
fXX: Main clock frequency
fXT: Subclock frequency
fCPU: CPU clock frequency
fCLK: Internal system clock frequency
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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