PD70F3826_15 Datasheet, PDF (30/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837 5. CLOCK GENERATION FUNCTION
5. CLOCK GENERATION FUNCTION
The clock generation function has the following features.
{ Main clock oscillator
• PLL mode (×8):
fX = 3 to 6.25 MHz (fXX = 24 to 50 MHz)
• Clock through mode: fX = 3 to 6.25 MHz (fXX = 3 to 6.25 MHz)
{ Subclock oscillator
• fXT = 32.768 kHz
{ Internal oscillator (fR = 220 kHz)
• Default clock of watchdog timer
• Sampling clock for clock monitor function of the main clock oscillator
• Can be used as the internal system clock after the main clock is stopped
{ Internal system clock generation
• 7 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT)
{ Peripheral clock generation
{ Clock output function
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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