PD70F3826_15 Datasheet, PDF (64/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
25. RESET FUNCTIONS
25. RESET FUNCTON
The following reset functions are available.
(1) Four types of reset sources
• External reset input via the RESET pin
• Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
• System reset by comparing the supply voltage and detection voltage by using the low-voltage detector (LVI)
• System reset by the clock monitor (CLM) upon detection of oscillation stop
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
The outline of the reset functions is shown below.
WDT2 reset signal
CLM reset signal
Internal bus
Reset source flag
register (RESF)
WDT2RF CLMRF LVIRF
Set
Set
Set
Clear
Clear
Clear
RESET
LVI reset signal
Remark LVIM: Low-voltage detection register
Reset signal
Reset signal to
LVIM register
Reset signal
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
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