PD70F3826_15 Datasheet, PDF (47/75 Pages) Renesas Technology Corp – RENESAS MCU

μ PD70F3826, 70F3827, 70F3828, 70F3829, 70F3830, 70F3831, 70F3832, 70F3833, 70F3834, 70F3835, 70F3836, 70F3837
15. ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
The number of UARTC of the V850ES/Jx3-E is shown below.
15. UARTC
Product Name
Number of channel
V850ES/JF3-E
3 channels
(UARTC0, UARTC2 and UARTC3)
V850ES/JF-E
4 channels
(UARTC0 to UARTC3)
V850ES/JG3-E
4 channels
(UARTC0 to UARTC3)
The UARTC has the following features.
{ Transfer rate: 300 bps to 3.125 Mbps (using internal system clock of 24 MHz and dedicated baud rate generator)
{ Full-duplex communication: On-chip UARTCn receive data register (UCnRX)
On-chip UARTCn transmit data register (UCnTX)
{ 2-pin configuration: TXDCn: Transmit data output pin
RXDCn: Receive data input pin
{ Reception error detect function
• Parity error
• Framing error
• Overrun error
• LIN communication data consistency error detect function
• SBF reception success detect function
{ Interrupt sources: 2 types
• Reception completion interrupt (INTUCnR): This interrupt occurs upon transfer of receive data from the receive
shift register to receive data register after serial transfer completion,
in the reception enabled status.
• Transmission enable interrupt (INTUCnT): This interrupt occurs upon transfer of transmit data from the transmit
data register to the transmit shift register in the transmission
enabled status.
{ Character length: 7, 8, 9 bits
{ Parity function: Odd, even, 0, none
{ Transmission stop bit: 1, 2 bits
{ On-chip dedicated baud rate generator
{ MSB-/LSB-first transfer selectable
{ Transmit/receive data inverted input/output possible
{ SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
possible
• 13 to 20 bits are selectable for SBF transmission
• Recognition of 11 bits or more possible for SBF reception in LIN format
• SBF reception flag provided
R01DS0029EJ0001 Rev.0.01
Sep 30, 2010
Page 47 of 75