M16C6K7 Datasheet, PDF (64/285 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.0
Watchdog Timer
Mitsubishi microcomputers
M16C / 6K7 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16
or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the
watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as
given below. The watchdog timer's period is, however, subject to an error due to the pre-scaler.
With XIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
With XCIN chosen for BCLK
Watchdog timer period =
pre-scaler dividing ratio (2) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the
pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a
watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Fig.DG-1 shows the block diagram of the watchdog timer. Fig.DG-2 shows the watchdog timer-related reg-
isters.
BCLK
HOLD
Write to the watchdog timer
start register
(address 000E16)
RESET
Prescaler
1/16
“CM07 = 0”
“WDC7 = 0”
1/128
“CM07 = 0”
“WDC7 = 1”
“CM07 = 1”
1/2
Watchdog timer
Set to
“7FFF16”
Watchdog timer
interrupt request
Fig.DG-1 Block diagram of watchdog timer
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