M16C6K7 Datasheet, PDF (142/285 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.0
PWM
Mitsubishi microcomputers
M16C / 6K7 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data Setup (PWM0)
The PWM0 output pin shares with P93 or P44. The PWM0 output pin is selected from either P93/PWM00 or
P44/PWM01 by bit 0 of PWM control register 0 (address 030816). The PWM0 output is enabled by setting bit
4 of PWM control register (address 030816) to "1". The PWM operation starts by setting bit 0 of PWM control
register 1 (address 030916) to "1". The high-order eight bits of output data are set in the PWM0H register
(address 030016) and the low-order six bits are set in the PWM0L register (address 030116). PWM1 to
PWM3 is set as the same way.
PWM Operation
The 14-bit PWM data is divided into the low-order six bits and the high-order eight bits in the PWM latch.
The high-order eight bits of data determine how long an “H”-level signal is output during each sub-period.
There are 64 sub-periods in each period, and each sub-period is 256 X τ (64 µs) long. The signal is “H” for a
length equal to N times τ, where τ is the minimum resolution (250 ns). “H” or “L” of the bit in the ADD part
shown in Fig. LA-2 is added to this “H” duration by the contents of the low-order 6-bit data according to the
rule in Table.LA-1. That is, only in the sub-period tm shown by Table.LA-1 in the PWM cycle period T = 64t,
its “H” duration is lengthened to the minimum resolution τ added to the length of other periods.
For example, if the high-order eight bits of the 14-bit data are 0316 and the low-order six bits are 0516, the
length of the “H”-level output in sub-periods t8, t24, t32, t40, and t56 is 4 τ, and its length is 3 τ in all other sub-
periods. Time at the “H” level of each sub-period almost becomes equal, because the time becomes length
set in the high-order 8 bits or becomes the value plus τ, and this sub-period t (= 64 µs approximate 15.6 kHz)
becomes cycle period approximately.
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch at each PWM period (every 4096 µs) and
data written to the PWMH register is transferred to the PWM latch at each sub-period (every 64 µs). The
signal which is output to the PWM output pin corresponds to the contents of this latch. A read from the PWML
gets the latch content. However, bit 7 of the PWML register indicates whether the transfer to the PWM latch
is completed; the transfer is completed when bit 7 is “0” and it is not done when bit 7 is “1.”
Table.LA-1 Relationship between low-order 6 bits of data and period set by the ADD bit.
Low-order 6 bits of data (PWML)
Sub-periods tm Lengthened (m=0 to 63)
0 0 0 0 0 0 LSB
None
000001
m=32
000010
m=16,48
000100
m=8,24,40,56
001000
m=4,12,20,28,36,44,52,60
010000
m=2,6,10,14,18,22,26,30,34,38,42,46,50,54,58,62
100000
m=1,3,5,7............................................................63
141