M16C6K7 Datasheet, PDF (59/285 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.0
________
INnMteIrrIunptetrrupt
Mitsubishi microcomputers
M16C / 6K7 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt 0
If the direction register of any of P50 to P57 is set for input and a falling edge is input to that port, a key input
interrupt 0 is generated. A key input interrupt 0 can also be used as a key-on wakeup function for cancelling
the wait mode or stop mode. Fig.DD-14 shows the block diagram of the key input interrupt 0. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Key Input Interrupt 1
If the direction register of any of P140 to P147 is set for input and a falling edge is input to that port, a key input
interrupt 1 is generated. The key input interrupt 1's function is equity to key input interrupt 0 except for the
valid falling edge input will be latched. When there is a valid falling edge input in P140 to P147 the corre-
sponding bit of P14 event register (Address : 02F616) will be set to "1". After interrupt request is generated,
the interrupt generated by "L" input can be conformed by reading the the register even the pin has been
returned to "H". A dummy write to the P14 event register clears the register to "0".
The block diagram of key input interrupt 1 is shown on Fig.DD-15 and the timing diagram of key input
interrupt 1 is shown on Fig.DD-16.
Pull-up
transistor
P57/KI07
P56/KI06
Pull-up
transistor
Pull-up
transistor
P55/KI05
P54/KI04
P53/KI03
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
P52/KI02
P51/KI01
P50/KI00
Pull-up
transistor
Pull-up
transistor
Pull-up select bit
Port P57 direction register
Port P57 direction register
Port P56 direction register
Port P55 direction
register
Port P54 direction
register
Port P53 direction register
Port P52 direction
register
Port P51 direction
register
Port P50 direction
register
Key input interrupt 0 control register _{(address 004D16)}
Interrupt control circuit
Key input interrupt 0
request
Fig.DD-14 Block diagram of key input interrupt 0
58