M16C6K7 Datasheet, PDF (144/285 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.0
PWM
Mitsubishi microcomputers
M16C / 6K7 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PWM0H
register
PWM0L
register
PWM0 latch
(14bits)
5916
Data 6A16 stored at address 030016
6A16
Data 7B16 stored at address 030016
7B16
Data 2416 stored at address 030116
Bit 7 cleared after transfer
Data 3516 stored at address 030116
1316
A416
2416
3516
165316
1A9316
Transfer from register to latch
1AA416
1AA416
B516
1EE416
Transfer from register to latch
1EF516
T = 4096 µs
(64 X 64 µs)
When bit 7 of PWM0L is 0, transfer
from register to latch is disabled.
t = 64 µs
Example 1 _{6A 6B 6A 6B 6A 6B 6A 6B 6A 6B 6B 6B 6A 6B 6A 6B 6A 6B 6A}
PWM0 output
1
low-order
6-bit output:
5
5
5
5
HL
6A16, 2416
6B16 ·············· 36 times
(107)
52 5
5
6A16 ············· 28 times
(106)
5
5
5
106 X 64 + 36
6B 6A 6B 6A 6B 6A 6B 6A
5
5
5
5
Example 2 _{6A 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A 6A 6B 6A 6B 6A 6B 6A 6A}
PWM0 output
6A 6B 6A 6B 6A 6B 6A 6A
low-order
6-bit output:
HL
6A16, 1816
4
3
6B16 ·············· 24 times
Minimum resolution bit width τ = 0.25 µs
4
4
3
6A16 ······· 40 times
t = 64 µs
(256 X 0.25 µs)
4
106 X 64 + 24
4
3
4
PWM output
2
8-bit
counter
6B 6A 69 68 67
ADD
02 01 00 FF FE FD FC
······· _{02 01}
······· _{97 96 95}
6A 69 68 67
ADD
······· _{02 01 00 FF FE FD FC}
······· _{02 01}
······· _{97 96 95}
·······
The ADD
portions with
additional τ are
determined by
PWML.
H duration length specified by PWM0H
256 τ (64 µs), fixed
Fig.LA-3 14-bit PWM timing (PWM0)
143