M16C6K7 Datasheet, PDF (212/285 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Rev.1.0
PS2 Interface
Mitsubishi microcomputers
M16C / 6K7 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
q PS2i Control register
• Reception enable bit (REN)
The data reception is allowed when this bit is set to “1”. The PS2 clock (CLK) will become to “H” (reception
enable status) automatically.
This bit will be cleared to “0” automatically after the completion of data reception and PS2 clock (CLK) will
become “L” (reception disable status) .
If this bit is needed wants to be cleared after setting it to “1” but before the transfer completion flag is
set, set reception enable bit = “0”, transfer abort request bit = “0” and proccess the transfer abort simultaneously.
• Transmission enable bit (TEN)
After writing transmission data to the PS2i shift register, setting the bit to “1” makes data transmission
enabled and PS2 clock (CLK) will become “H” automatically (transmission enable status).
This bit will be cleared to “0” automatically after the completion of data transmission and PS2 clock (CLK)
will become “L” (transmission disable status).
If this bit is needed to be cleared after setting it to “1” but before the transfer completion flag is set, set
reception enable bit = “0”, transfer abort request bit = “0” and proccess the transfer abort simultaneously.
• Transfer abort request bit (RSTOP)
This bit is used to abort the data transfer procession.
At the completion of transfer abort procession, the transfer completion flag and transfer abort flag of
PS2i status register are set to “1”, the bit is cleared to “0” automatically and PS2 clock (CLK) will become
“L” ( reception disable status).
After “L” is output to the PS2 clock (CLK), do not execute the following transmission/reception before the
device recognizes the transfer abort request.
PS2i control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PS20CON
PS21CON
PS22CON
Address
02A216
02A616
02AA16
Bit Symbol
REN
Bit name
Reception enable bit
TEN
RSTOP
Transmission enable bit
Transfer abort request bit
Nothing is allocated.
Meaningless in writing, "0" in reading.
Reset Value
0016
0016
0016
Function
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : No transfer abort
1 : Transfer abort
Fig.GK-6 PS2i control register
RW
211