HD66773R Datasheet, PDF (63/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
Serial Peripheral interface (SPI)
The Serial Peripheral Interface (SPI) becomes operable by setting IM3/2/1 pins to GND/Vcc/GND levels
respectively. The SPI is available through the chip select line (CS*), serial transfer clock line (SCL), serial
data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the
SPI mode, the unused DB15-2 pins must be fixed at either Vcc or GND level.
The HD66773R recognizes the start of data transfer at the falling edge of CS* input to initiate the transfer
of a start byte. It recognizes the end of data transfer at the rising edge of CS* input. The HD66773R is
selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit
device identification code assigned to the HD66773R are compared and the both 6-bit data correspond.
When selected, the HD66773R starts taking in the subsequent data string. The setting for the least
significant bit of the identification code is made with the ID pin. The five upper bits of the identification
code must be 01110. Two different chip addresses must be assigned to the HD66789 because the seventh
bit of the start byte is assigned to a register select bit (RS). When RS = 0, index register write or status read
is executed. When RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte
is to specify read or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when
the R/W bit is 1.
In the SPI mode, the data are written to GRAM after the two-byte data transmission. The data are
expanded into 18 bits by adding one bit (the same data as the MSB of RB) next to the LSB of RB data.
After receiving the start byte, the HD66773R starts data transmission/reception by byte. The data
transmission adopts the format which the MSB is first transmitted. All HD66773R instructions consist of
16 bits and they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0).
The data to be written to RAM are expanded into 18-bit data. After the start byte is received, the upper
eight bits of the instruction are always fetched as the first byte, and the lower eight bits of the instruction
are always fetched as the second byte. The 4-byte data that are read from RAM right after the start byte are
made invalid. The HD66773R reads as valid data from the 5th-byte data.
Start Byte Format
Transmitted bits
S
1
2
3
4
5
6
7
8
Start byte format
Transmission Device ID code
start
RS R/W
0
1
1
1
0
ID
Note 1) ID bit is selected with the IM0/ID pin.
RS and R/W Bit Function
RS R/W Function
0
0
Set index register
0
1
Read status
1
0
Write instruction or RAM data
1
1
Read instruction or RAM data
Rev.1.10, Jun.21.2003, page 63 of 133