HD66773R Datasheet, PDF (119/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
Normal Write Mode (HWM=0) (Vcc = 2.4 to 3.3 V)
Item
Bus cycle time
Write low-level pulse width
Read low-level pulse width
Write high-level pulse width
Read high-level pulse width
Write/Read rise/fall time
Set up time
(RS to CS*, WR*, RD*)
Symbol
Write
Read
t_CYCW
t_CYCR
PW_LW
PW_LR
PW_HW
PW_HR
t_{WRr, WRf}
Unit
ns
ns
ns
ns
ns
ns
ns
t_AS
ns
Address hold time
Write data setup time
Write data hold time
Read data delay time
Read data hold time
t_AH
ns
t_DSW
ns
t_HWR
ns
t_DDR
ns
t_DHR
ns
Timing
diagram
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Min Typ Max Notes
200 — —
300 — —
40 — —
150 — —
100 — —
100 — —
— — 25
10
—
—
with status
read
0
—
—
without
status read
2 ——
60 — —
2 ——
— — 100
5 ——
High-Speed Write Mode (HWM=1) (Vcc = 2.4 to 3.3 V)
Item
Bus cycle time
Write low-level pulse width
Read low-level pulse width
Write high -level pulse width
Read high -level pulse width
Write/Read rise/fall time
Symbol Unit
Write t_CYCW
ns
Read t_CYCR
ns
PW_Lw
ns
PW_LR
ns
PW_HW
ns
PW_HR
ns
t _WRr, _WRf
ns
Timing
diagram
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Set up time
(RS to CS*, WR*, RD*)
Figure 2
t_AS
ns
Figure 2
Address hold time
Write data set up time
Write data hold time
Read data delay time
Read data hold time
t_AH
ns
t_DSW
ns
t_HWR
ns
t_DDR
ns
t_DHR
ns
Figure 2
Figure 2
Figure 2
Figure 2
Figure 2
Min Typ Max Notes
100 — —
300 — —
40 — —
150 — —
40 — —
100 — —
— — 25
10
—
—
with status
read
0
without
status read
2 ——
60 — —
2 ——
— — 100
5 ——
Rev.1.10, Jun.21.2003, page 119 of 133