HD66773R Datasheet, PDF (54/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
Reset Function
The HD66773R makes internal initial settings with RESET input. During the RESET, the HD66773R is in
a busy state, and no instructions from the MPU and access to GRAM are accepted. The time required for
the RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on
until the R-C oscillation frequency becomes stabilized. While waiting, do not make initial settings for the
instruction set, nor access to GRAM.
Initial State of Instructions
a. Start oscillation
b. Driver output control (NL4–0 = “10101”, SS = “0”, CS = “0”)
c. Liquid crystal AC drive control (FLD1-0 = “01”, B/C = “0”, EOR = “0”, NW5–0 = “00000”)
d. Power control 1 (BT2-0 = “000”, DC2–0 = “000”, AP2–0 = “000”: liquid crystal power supply off,
SLP = “0”, STB = “0” : Standby mode off)
e. Power control 2 (CAD = “0”)
f. Entry mode set (DIT = “0”, BGR = “0”, HWM = “0”, I/D1-0 = “11”: Increment by 1,
AM = “0”: Horizontal direction, LG2–0 = “000”: Replace mode)
g. Compare register (CP15–0 : “0000 0000 0000 0000”)
h. Display control (PT1-0 = “00”, VLE2-1 = “00”: No vertical scroll,
SPT = “0”, GON = “0”, DTE = “0”, CL = “0”: 262,144 colors,
REV = “0”, D1-0 = “00”: Display OFF)
i. Power control 3 (VC2-0 = “000”)
j. Power control 4 (VRL3-0 = “0000”, PON = “0”, VRH3-0 = “0000”)
k. Power control 5 (VDV4-0 = “00000”, VCOMG = “0”, VCM4-0 = “00000”)
l. Frame cycle control (NO1-0 = “00”, SDT1-0 = “00”, EQ1-0 = “00” : No equalization,
DIV1-0 = “00”: clock/1, RTN3-0 = “0000” : 16 clocks in 1H period)
m. Gate scan starting position (SCN4-0 = “00000”)
n. Vertical scroll (VL7–0 = “00000000”)
o. 1st split-screen (SE17-10 = “11111111”, SS17-10 = “00000000”)
p. 2nd split-screen (SE27-20 = “11111111”, SS27-20 = “00000000”)
q. Horizontal RAM address position (HEA7-0 = “10000011”, HSA7-0 = “00000000”)
r. Vertical RAM address position (VEA7-0 = “10101111”, VSA7-0 = “00000000”)
s. RAM write data mask (WM15–0 = “0000”H: No mask)
t. RAM address set (AD15–0 = “0000”H)
u. γ control
(PKP02-00 = “000”, PKP12-10 = “000”, PKP22-20 = “000”, PKP32-30 = “000”,
PKP42-40 = “000”, PKP52-50 = “000”, PRP02-00 = “000”, PRP12-10 = “000”)
(PKN02-00 = “000”, PKN12-10 = “000”, PKN22-20 = “000”, PKN32-30 = “000”,
PKN42-40 = “000”, PKN52-50 = “000”, PRN02-00 = “000”, PRN12-10 = “000”)
(VRP14-10 = “00000”, VRP03-00 = “0000”, VRN14-10 = “00000”, VRN12-10 = “000”)
GRAM Data Initialization
The data in GRAM are not initialized with the RESET input. Initialize through software during the display
OFF (D1–0 = “00”).
Rev.1.10, Jun.21.2003, page 54 of 133