HD66773R Datasheet, PDF (30/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
DC2–0: Select the operating frequency for the step-up circuit. The higher step-up frequency enhances the
drive capacity of step-up circuit as well as the display quality, while the current consumption will increase.
Adjust the frequency taking both the display quality and the current consumption into consideration.
DC2 DC1 DC0
000
001
010
011
100
101
110
111
Step-up Cycle of Step-up Circuit 1
DCCLK /16
DCCLK / 32
DCCLK / 64
DCCLK / 32
DCCLK / 16
DCCLK / 32
DCCLK / 64
DCCLK / 64
Step-up Cycle in Step-up Circuits 2/3/4
DCCLK / 64
DCCLK / 64
DCCLK / 64
DCCLK / 256
DCCLK / 128
DCCLK / 128
DCCLK / 128
DCCLK / 256
AP2–0: Adjust the amount of fixed current from the fixed current source in the operational amplifier circuit
in the liquid crystal drive power supply. When the amount of fixed current is set large, the liquid crystal
drive capacity is enhanced and the display quality will improve, while the current consumption will
increase. Select an optimum amount of current taking both the display quality and the current consumption
into account. During non-display operation, set AP2-0 = “000” to halt the operation of operational
amplifier and step-up circuit to further reduce current consumption.
AP2 AP1 AP0 Amount of Current in Operational Amplifier
0
0
0 Halt operational amplifier and step-up circuit
0
0
1 Small
0
1
0 Small or medium
0
1
1 Medium
1
0
0 Medium or large
1
0
1 Large
1
1
0 Setting disabled
1
1
1 Setting disabled
SLP: When SLP = 1, the HD66773R enters into the sleep mode. In the sleep mode, internal display
operation is halted except the R-C oscillator to reduce current consumption. No change is made to the
GRAM data or instructions during the sleep mode, but it is retained.
STB: When STB = 1, the HD66773R enters into the standby mode. In the standby mode, display operation
is completely halted, and all internal operation including the internal R-C oscillator and reception of
external clock pulse, is halted. For details, see “Standby Mode”. Only instructions to access R03h
including the standby bit and to start oscillation are accepted during the standby mode.
CAD: Make an appropriate setting for the structure of TFT panel holding capacitor.
Set CAD = “0” for Cst structure.
Set CAD = “1” for Cadd structure.
Rev.1.10, Jun.21.2003, page 30 of 133