HD66773R Datasheet, PDF (59/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
9-bit interface
68-system 9-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to
Vcc/GND/GND/Vcc levels respectively throughDB17-9 pins. 80-system 9-bit parallel data transmission
becomes operable by setting IM3/2/1/0 pins to Vcc/GND/Vcc/Vcc levels respectively throughDB17-9 pins.
The 16-bit instruction is divided into 2 8-bit data and upper 8-bit data is transferred first. The LSB is not
used for each upper/lower-bit data transfer. The 18-bit RAM data is also divided into 2 9-bit data and
upper 9-bit data is transferred first. The unused pins DB8-0 must be fixed to either “Vcc” or “GND”. The
upper-byte write is also required when writing index registers. The data transfer through 9-bit mode is
effective only for write mode, and not effective for read operation.
9-bit bus interface
H8/2245
CSn*
A1
HWR*
(RD*)
D15 - 0
9
9
GND
CS*
RS
WR*
HD66773R
(RD*)
DB17 – 9
DB8-0
Data format for 9-bit bus interface
Instr uction
Input
First transfer (upper)
Second transfer (lower)
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Instruction
IB
15
IB
14
IB
13
IB
12
IB
11
IB
10
IB
9
IB
8
IB IB IB IB IB IB IB IB
7 654 321 0
Instruction code
RAM data write
First transfer (upper)
Second transfer (lower)
Input _{DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB}
17 16 15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9
Dither process _{HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD HD}
circuit _{17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
Shrinking
Shrinking
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R,G,B assignment _{R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0}
1 pixel
Note: 262,144 colocs available with 9-bit system interface by setting DIT bit to "1".
Rev.1.10, Jun.21.2003, page 59 of 133