HD66773R Datasheet, PDF (13/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
Signals
VcomH
VcomL
VgoffOUT
Vgoff
VgoffH
VgoffL
V0P
V31P
V0N
V31N
VGS
S1–S396
G1-176
GTEST1-2
TESTA1
TESTA2
TESTA3
Number
of Pins
1
1
1
1
1
1
2
2
1
396
176
2
1
1
1
I/O Connected Functions
to
O Stabilizing Vcom high level generated during Vcom AC drive. Connect to a
Capacitor stabilizing capacitor.
O Stabilizing The Vcom level without Vcom AC drive, and Vcom low level with
Capacitor or Vcom AC drive. The voltage can be adjusted with internal register
open
setting. Connect to a stabilizing capacitor. VcomL output is
halted when VCOMG bit is LOW, and in this case, stabilizing
capacitor is not necessary.
O Vgoff or
Open
Output power supply for gate drive. Internal register setting
enables AC drive in synchronization with Vcom. Make an
appropriate setting for the structure of hold capacitor of TFT
display. Output the amplitude VcomH-VcomL in reference to
VgoffL with AC drive.
I VgoffOUT or TFT gate off level. Negative voltage. Connect to VgoffOUT or
power
otherwise, connect to external voltage power supply of VGL or
supply
more.
O Stabilizing VgoffOUT high level with Vgoff AC drive. Connect to a stabilizing
Capacitor or capacitor. The Vgoff output is halted when CAD bit is LOW. In
open
this case, no stabilizing capacitor is necessary.
O Stabilizing VgoffOUT without Vgoff AC drive, and VgoffOUT low level with
Capacitor Vgoff AC drive. The voltage can be adjusted with internal register
setting. Connect to a stabilizing capacitor.
I/O Stabilizing
Capacitor
Output from positive-polarity internal operational amplifier when
the internal operational amplifier is turned on. Connect to a
stabilizing capacitor.
I/O Stabilizing
Capacitor
Output from negative-polarity internal operational amplifier when
the internal operational amplifier is turned on. Connect to a
stabilizing capacitor.
I GND or
external
resistor
Reference voltage for grayscale voltage generating circuit. Place
a variable resistor externally when adjusting a level for each
panel.
O LCD
Source output signal. The shift direction of segment signal is
changeable with SS bit:
SS = 0, RAM address 0000 is output from S1.
SS = 1, it is output from S396.
S1, S4, S7, ... display red (R), S2, S5, S8, ... display green (G),
and S3, S6, S9, ... display blue (B) (SS = 0).
O LCD
Gate output signal. Output VGH level to select a gate line, and
output Vgoff level not to select a gate line.
O LCD or
Open
Dummy gate output signal. Output the VGH level to select a gate
line, and output the Vgoff level not to select a gate line when CAD
bit is High. Output the Vgoff level not to select a gate line when
CAD bit is Low. Leave open when not used.
I/O Stabilizing A test pin for the VcomH output. Leave it open or connect to a
Capacitor or stabilizing capacitor if necessary depending on the quality of
Open
display.
I/O Stabilizing A test pin for the VcomL output. Leave it open or connect to a
Capacitor or stabilizing capacitor if necessary depending on the quality of
Open
display.
I/O Stabilizing A test pin for the Vgoff output. Leave it open or connect to a
Capacitor or stabilizing capacitor if necessary depending on the quality of
Open
display.
Rev.1.10, Jun.21.2003, page 13 of 133