HD66773R Datasheet, PDF (41/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in
synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. When
changing the number of drive raster-rows, adjust the frame frequency too. For details, see “Frame
Frequency Adjustment Function”.
DIV1 DIV0 Division Ratio
0
0
1
0
1
2
1
0
4
1
1
8
fosc = R-C oscillation frequency
Internal Operating Clock Frequency
fosc / 1
fosc / 2
fosc / 4
fosc / 8
Formula for the frame frequency
Frame frequency
fosc
[Hz]
Clock cycles per raster-row × division ratio × (Line + 8)
fosc: R-C oscillation frequency
Line: number of drive raster-rows (NL bit)
Division ratio: DIV bit
Clock cycles per raster-row: RTN bit
EQ1-0: Set the period for equalization, where Vcom output becomes Hi-z.
EQ1 EQ0
Equalizing period
0
0
Not equalized
0
1
1 clock
1
0
2 clocks
1
1
3 clocks
Note) Equalizing is valid while VcomL is 0V or more. Otherwise, set EQ = “00”
Rev.1.10, Jun.21.2003, page 41 of 133