HD66773R Datasheet, PDF (42/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
SDT1-0: Determine the amount of delay for the source output from the falling edge of the gate output.
SDT1
0
0
1
1
SDT0
0
1
0
1
Delay Time for Source Signal
1 clock
2 clocks
3 clocks
4 clocks
1H period
Gn
1H period
Sn
EQ
Delay amount of
the source output
Equalizing period
NO1-0: Specify the amount of non-overlap time for the gate output.
NO1
0
0
1
1
NO0
0
1
0
1
0 clock
4 clocks
6 clocks
8 clocks
Non-overlap time
Gn
Gn+1
1H period
Non-overlap period
1H period
Rev.1.10, Jun.21.2003, page 42 of 133