HD66773R Datasheet, PDF (46/133 Pages) Renesas Technology Corp – 262,144-color, 132 x 176-dot Graphics Controller Driver for TFT LCD panels

HD66773R
RAM Write Data Mask (R20h)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
WM _{WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM}
15 _{14 13 12 11 10 9 8 7 6 5 4}
321 0
WM15–0: Write-mask the data when written to GRAM by bit. The write-mask function is available with
8/16-bit interface modes. For example, if WM15 = 1, the data in WD15 bit is write-masked so that it is not
written to GRAM. The rest of WM14-0 bits also write-mask the data in the corresponding WD bits when
these bits are set to “1”. For details, see “Graphics Operation Function”.
RAM Address Set (R21h)
R/W RS
W1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD AD
15 14 13 12 11 10 9 8 7 6 5 4
32
10
AD15–0: Make a GRAM address initial setting in the address counter (AC). After GRAM data are written,
the address counter is automatically updated according to the settings with AM, I/D bits and the setting for
a new GRAM address is not required in the address counter. Therefore, data are written consecutively
without resetting the address. The address counter is not automatically updated when data are read out
from GRAM.
GRAM address setting can not be made during the standby mode. An address set should be made within
the area specified with the window address.
GRAM Address Range
AD15–AD0
“0000”H – “0083”H
“0100”H – “0183”H
“0200”H – “0283”H
“0300”H – “0383”H
:
“AC00”H – “AC83”H
“AD00”H – “AD83”H
“AE00”H – “AE83”H
“AF00”H – “AF83”H
GRAM Setting
Bitmap data for G1
Bitmap data for G2
Bitmap data for G3
Bitmap data for G4
:
Bitmap data for G173
Bitmap data for G174
Bitmap data for G175
Bitmap data for G176
Rev.1.10, Jun.21.2003, page 46 of 133