PD70F3461_15 Datasheet, PDF (58/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

9. Revision History
µPD70F3461
This document is the first release of the V850CAG4-M Datasheet. The revision history of
U18578EE1V0DS00 refers to the V850E/CAG4-M Electrical Target Specification EASE-ES-0009 V0.4.
Version Chapter
1
2
3
V.1.0
4
6
7
Page
12
16
17
18
25
27
28
30
33
33 - 35
-
48-51
52
54
Remarks
• Specification for storage temperature in Table 1-1 added
• Max. value for T_OST removed, replaced by typ.
• Note regarding T_OST added
• Specification for T_SOST removed from Table 2-2
• Note regarding T_SOST added
CPU PLL output period jitter added to Table 2-4
Chapter ’DC Characteristics for Pins Influenced by Injected Current on Adjacent
Pin’ removed
Table 4-1: Turning On / Interception Timing
• t_WMRGD removed, not applicable, timing included in t_WMRPD
• t_WMRPD min. timing added
Table 4-2: Turning On / Interception Timing
• t_WRPD min. timing added
• Table footer d) reference to main oscillator removed; not applicable for
RESET
CSIB Table 4-4 and Table 4-5 timings added
CSIE timings
• Caution regarding load added
• Figure 4-12 CSIE AC Load Condition added
Table 4-6 and Table 4-7 timings added
Chapter ’External Asynchronous Memory’ removed
Flash Memory Characteristics; complete chapter extended
• Code Flash Memory Characteristics
• Data Flash Memory Characteristics
• Specification for storage temperature in Table 7-1 added
• Restriction for use of 32KHz sub-oscillator bellow 4.5V removed
Table 7-7: Turning On / Interception Timing
• t_WRPD min. timing added
Datasheet U18578EE1V0DS00
60