PD70F3461_15 Datasheet, PDF (28/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

4.2 Reset of Isolated Area: RESET Timing
T_A =-40 to +105°C
V_DD5X = 4.5 to 5.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
µPD70F3461
Table 4-2: Turning On / Interception Timing
Parameter
Symbol
Conditions
MIN.
TYP.
MAX. Unit
RESET high-level width ^a
t_WRSH
300
ns
RESET low-level width ^b
t_WRSLIL
300
ns
RESET pulse rejection ^c
t_WRRJ
140
200
350
ns
RESET power up delay ^d
t_WRPD
2
ms
a. This signal high time is needed to ensure that the internal RESET release operation starts.
b. This signal low time is needed to ensure that the internal RESET is activated.
c. The RESET input incorporates an analog filter. Pulses shorter than this value will be ignored. Char-
acteristic is not tested during production, it is ensured by design and will be evaluated.
d. During ramp-up of the internal power supply (VDD of the main area) the release of RESET has to
be delayed until VDD is stabilized.
RESET
Figure 4-3: RESET timing
t_WRSH
t_WRSL
Figure 4-4: RESET delay during VDD ramp-up
VDD5x
RESET
t_WRPD
Datasheet U18578EE1V0DS00
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