PD70F3461_15 Datasheet, PDF (44/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

4.10 MediaLB Timing
µPD70F3461
T_A =-40 to +105°C
V_DD5X = 4.5 to 5.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
The AC characterics of the MediaLB of following table is considered with a load capaticance of 40 pF.
Table 4-12: MediaLB Timing
Parameter
Symbol
Conditions
MIN. TYP. MAX. Unit
256 x FS at 44.0 KHz 11.264
256 x FS at 48.0 KHz
12.228
MLBCLK operating frequencies f_MCK
512 x FS at 44.0 KHz
24.576
MHz
512 x FS at 48.1 KHz
24.627
512 x FS PLL unlocked
25.600
MLBCLK rise time
t_MCKR
3
ns
MLBCLK fall time
t_MCKF
3
ns
MLBCLK cycle time
t_MCKC
256 x FS
512 x FS
81
ns
40
256 x FS
31.5
37
ns
256 x FS PLL unlocked
30
35.5
MLBCLK low time
t_MCKL
512 x FS
14.5
17
ns
512 x FS PLL unlocked
14
16.5
256 x FS
31.5
38
ns
256 x FS PLL unlocked
30
36.5
MLBCLK high time
t_MCKH
512 x FS
14.5
17
ns
512 x FS PLL unlocked
14
16.5
MLBCLK pulse width variation t_MPWV
a
2
ns pp
MLBSIG/MLBDAT input valid
(vs. MLBCLK falling)
t_DSMCF
1
ns
MLBSIG/MLBDAT input hold
(vs. MLBCLK low)
t_DHMCF
0
ns
MLBSIG/MLBDAT output high
impedance (vs. MLBCLK low)
t_MCFDZ
0
t_MCKL
ns
Bus hold time
t_MDZH
4
ns
MLBSIG/MLBDAT output valid
(vs. MLBCLK rising)
t_DSMCH
13
ns
a. Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring
the spread on the other edge, measured in ns peak-to-peak (pp)
Datasheet U18578EE1V0DS00
44