PD70F3461_15 Datasheet, PDF (41/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

µPD70F3461
4.6 I²C Characteristics
T_A =-40 to +105°C
V_DD5X = 4.5 to 5.5V
V_DD3x = AV_DD = BV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
Table 4-8: I²C Characteristics
Parameter
Symbol
Normal Mode
Fast Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
f_CLK
0
100
0
400
kHz
Bus-free time (between stop/start conditions) t_BUF
4.7
1.3
µs
Hold time ^a
t_HD:STA
4.0
0.6
µs
SCL0 clock low-level width
t_LOW
4.7
1.3
µs
SCL0 clock high-level width
t_HIGH
4.0
0.6
µs
Setup time for start/restart conditions
t_SU:STA
4.7
0.6
µs
CBUS compatible master
5.0
µs
Data hold time
I²C mode
t_HD:DAT
0^b
3.45 ^c
0^b
0.9 ^c
µs
Data setup time
t_SU:DAT
250
100 ^d
ns
STOP condition setup time
t_SU:STO
4.0
0.6
µs
Noise suppression ^e
t_SP
t_IICLK ^f
µs
Capacitive load of each bus line
C_b
400
400
pF
a. At the start condition, the first clock pulse is generated after the hold time.
b. The system requires a minimum of 300ns hold time internally for the SDA signal (at V_IHmin of SCL0
signal) in order to occupy the undefined area at falling edge of SCL0.
c. If the system does not extend the SCL0 signal low time (t_low), only the maximum data hold time
(t_HD:DAT) needs to be satisfied.
d. The fast-speed-mode IIC bus can be used in a normal-mode IIC bus system. In this case, set the
fast-speed-mode IIC bus so that it meets the following conditions:
- If the system does not extend the SCL0 signals low state hold time:
t_SU:DAT ≥250ns
- If the system extends the SCL0 signal low state hold time:
Transmit the following data bit to the SDA0 line prior to releasing the SCL0 line
(t_Rmax + t_SU:DAT = 1000+250 ns = 1250ns : Normal mode IIC bus specification).
e. Noise suppresion is only available in fast-speed mode.
f. t_IICLK is the period of the IICLK supplied by the clock controller.
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Datasheet U18578EE1V0DS00