PD70F3461_15 Datasheet, PDF (33/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

µPD70F3461
4.5 Enhanced Queued Clocked Serial Interface (CSIE) Timing
T_A =-40 to +105°C
V_DD5X = 4.5 to 5.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
Cautions: 1.
2.
All output pins used for CSIE application (CSIE0 [ports P40, P41] and CSIE1
[PDL14, PDL15] are connected to an external load of 50pF.
All chip select output pins for the CSIE (SCSE00 to 07 [PAL7 to 14] and SCSE10 to
13 [PAL3 to 6] are connected to an external load of 25pF.
Figure 4-10: CSIE AC Load Condition
DUT
CSIE Application Load
CL=50pF (SIEn, SCLKn)
CL
CL=25pF (SCSCE00 to 07,
SCSCE10 to 13)
Table 4-6: CSIE Characteristics (Master Mode)
Parameter
Macro operation clock, cycle time
SCKEn cycle time
SCKEn high level width
SCKEn low level width
SIEn input setup time (vs. SCKEn)
SIEn input hold time (vs. SCKEn)
SOEn output delay (vs. SCKEn)
SOEn output hold time (vs. SCKEn)
SCSEnm inactive (High) width
CEnSIT=x
CEnOPE=0
CEnMD=x
CEnSIT=x
CEnOPE=1
CEnMD=x
Symbol
t_KCY
t_KCYM
t_KWHM
t_KWLM
t_SSI
t_HSIM
t_DSOM
t_HSOM
t_WSCSB0
t_WSCSB1
MIN.
31.25
125
t_KCYM/2 - 10
t_KCYM/2 - 10
20
10
t_KCYM/2 - 10
t_KCYM/2 - 10
(CS_IDLE + 0.5)*t_KCYM - 10
MAX.
Unit
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
33
Datasheet U18578EE1V0DS00