PD70F3461_15 Datasheet, PDF (27/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

µPD70F3461
4.1 Reset of Main Area: MRESET Timing
T_A =-40 to +105°C
V_DD5X = 4.5 to 5.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
Table 4-1: Turning On / Interception Timing
Parameter
Symbol
Conditions
MIN.
TYP.
MAX. Unit
MRESET high-level width ^a
t_WMRSH
200
ns
MRESET low-level width ^b
t_WMRSLIL
200
ns
MRESET pulse rejection ^c
t_WMRRJ
50
100
200
ns
MRESET power up delay ^d
t_WMRPD
2 + T_OST
ms
a. This signal high time is needed to ensure that the internal MRESET release operation starts.
b. This signal low time is needed to ensure that the internal MRESET is activated.
Reset pulses shorter than the given value may not be recognized by the device
c. The MRESET input incorporates an analog filter. Pulses shorter than this value will be ignored.
Characteristic is not tested during production, it is ensured by design and will be evaluated.
d. During ramp-up of the internal power supply (VDD of the main area) the release of
MRESET has to be delayed until VDD and the main oscillator are stabilized.
Please also refer to chapter 2.1 on page 16.
MRESET
Figure 4-1: MRESET timing
t_WMRSH
t_WMRSL
Figure 4-2: MRESET delay during VDD ramp-up
VDD3x
REGC3x
MRESET
t_WMRGD
t_WMRPD
27
Datasheet U18578EE1V0DS00