PD70F3461_15 Datasheet, PDF (34/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

µPD70F3461
Table 4-6: CSIE Characteristics (Master Mode)
Parameter
Symbol
MIN.
MAX.
Unit
CEnSIT=x
CEnOPE=0
CEnIDL=x
t_SSCSB0
t_KCY - 10
ns
CEnMD=0
CEnSIT=x
CEnOPE=1
CEnIDL=0
t_SSCSB1
t_KCYM + t_KCY - 10
ns
CEnMD=0
CEnSIT=x
CEnOPE=0
SCSEnm setup time (vs.
CEnWE=1
CEnCSM=1
t_KCYM / 2 + t_KCY - 10
ns
SCKEn)
CEnIDL=x
CEnMD=x
CEnSIT=x
CEnOPE=1
(CEnIDL=0
t_SSCSB2
and CS
change)
CEnMD=X
CS_SETUP * t_KCYM + t_KCY - 10
ns
CEnSIT=x
CEnOPE=1
CEnIDL=1
CEnMD=X
CEnSIT=0
ns
CEnOPE=0 t_HSCSB0
t_KCY - 10
CEnMD=x
CEnSIT=1
ns
SCSEnm hold time (vs.
CEnOPE=0
CEnMD=x
t_HSCSB1
t_KCYM/2 + t_KCY - 10
SCKEn)
CEnSIT=0
ns
CEnOPE=1
CEnMD=x
t_HSCSB2
CS_HOLD * t_KCYM + t_KCY - 10
CEnSIT=1
CEnOPE=1
CEnMD=x
t_HSCSB3
(CS_HOLD + 0.5)* t_KCYM + t_KCY -
10
ns
CEnSIT=x
ns
SCSEnm interframe time
CEnOPE=1
CEnMD=x
t_INTER
CS_INTER * t_KCYM - 5
CEnSIT=x
ns
CEnOPE=0
-
Not Applicable
CEnMD=x
Remark:
n=0,1
m=7-0(n=0),3-0(n=1)
CS_SETUP,CS_INTER: are set by register CEnOPT0
CS_IDLE,CS_HOLD: are set by register CEnOPT1
Datasheet U18578EE1V0DS00
34