PD70F3461_15 Datasheet, PDF (54/63 Pages) Renesas Technology Corp – V850E/CAG4-M 32-Bit Single-Chip Microcontroller

µPD70F3461
(5) Input/Output Level Pin Group 13: Isolated Area FLMD0
These pins are supplied with V_DD5X with the same I/O characteristics.
Pin of this pin group is:
- FLMD0
Table 7-5: Input/Output Level Pin Group 13
Parameter
Input voltage,high
Input voltage,low
Symbol
V_IH13
V_IL13
Conditions
MIN.
TYP. MAX. Unit
0.8 x V_DD50
V_DD5X+0.3 V
-0.5
0.2 x V_DD50 V
(6) Supply Current
T_A =-40 to +105°C
V_DD50 = 3.15 to 4.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
Table 7-6: Power Supply Current
Parameter
Conditions
Supply
Pins^{a Symbol MIN.}
TYP.^b
MAX.
Unit
Supply
current^c
RUN mode
(f_CPU = 80MHz, PLL: on)
Power down mode ^{TA= 25°C}
main area power-off T_A= 85°C
isolated area stand-by _{TA= 105°C}
VDD50
VDD50
I_DD1IA
I_DD5IA
1.2
mA
55
µA
300
µA
600
µA
a. n= 0 to 2
b. The typical value refers to Ta = 25°C, V_DD50 = 5V and V_DD3n
c. The port output current resulting from built-in pull-up or pull-down resistances is not included.
(7) AC Characteristic: RESET Timing
T_A =-40 to +105°C
V_DD5X = 3.15 to 4.5V
V_DD3x = AV_DD = BV_DD3x = MV_DD3x = 3.0 to 3.6V
V_SS5X = V_SS3x = AV_SS = BV_SS5X = BV_SS3X = MV_SS3X = 0V
Table 7-7: Turning On / Interception Timing
Parameter
Symbol
Conditions
MIN.
TYP.
MAX. Unit
RESET high-level width ^a
t_WRSH
300
ns
RESET low-level width ^b
t_WRSLIL
300
ns
RESET pulse rejection ^c
t_WRRJ
140
200
350
ns
RESET power up delay ^d
t_WRPD
2
ms
a. This signal high time is needed to ensure that the internal RESET release operation starts.
b. This signal low time is needed to ensure that the internal RESET is activated.
c. The RESET input incorporates an analog filter. Pulses shorter than this value will be ignored. Char-
acteristic is not tested during production, it is ensured by design and will be evaluated.
d. During ramp-up of the internal power supply (VDD of the main area) the release of RESET has to
be delayed until VDD and the main oscillator are stabilized.
Note: For figures please refer to 4.2 ”Reset of Isolated Area: RESET Timing” on page 28
Datasheet U18578EE1V0DS00
54