PD77210_15 Datasheet, PDF (54/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

Standby mode status output timing
Internal clock
Internal status
Execution STOP or
HALT Instruction
µPD77210, 77213
Fetch Next Instruction
of STOP or HALT
CSTOP
STOPS
HALTS
tdSTP
tdHLT
tdHLT
Remarks 1. Internal clock cycle is changed or stopped to be fixed to low level when STOP or HALT mode.
2. STOPS pin is become low level asynchronously by CSTOP pin rising edge.
Timer time out status output timing
Internal clock
Internal status
TIMOUT
Detect Time out
tdTIM
twTIM
tdTIM
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Data Sheet U15203EJ3V0DS