PD77210_15 Datasheet, PDF (49/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
DC Characteristics (Unless otherwise specified, TA = − 20 to + 70°C, with IVDD and EVDD within recommended
operating condition range)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
High level input voltage
VIHN
Pins other than below
0.7 EVDD
EVDD
V
VIHC
CLKIN
0.7 EVDD
EVDD
V
VIHS
RESET, P0 to P15, TSCK,
0.8 EVDD
TSIEN,TSOEN, ASCK, ASIEN,
ASOEN
EVDD
V
Low level input voltage
VILN
Pins other than below
0
0.2 EVDD
V
VILC
CLKIN
0
0.2 EVDD
V
VILS
RESET, P0 to P15, TSCK,
0
TSIEN,TSOEN, ASCK, ASIEN,
ASOEN
0.2 EVDD
V
High level output voltage
VOH
IOH = −100 µA
0.8 EVDD
V
Low level output voltage
VOL
IOL = 2.0 mA
0.2 EVDD
V
High level input leakage
current
ILHN
VI = EVDD
0
10
µA
Low level input leakage
current
ILLN
VI = 0 V
−10
0
µA
High impedance leakage
ILZ
current
0 V ≤ VI ≤ EVDD
0
−10
µA
Pull-up pin current
IPUI
TDI, TMS, 0 V ≤ VI ≤ EVDD
20
70
200
µA
Pull-down pin current
IPDI
TRST, 0 V ≤ VI ≤ EVDD
−20
−70
−200
µA
Internal supply current
IDD
During operating,
[fclkin = 10 MHz,
fclk = 100 MHz,
IVDD = 1.5 V,
PLL multiple rate x10
VIHN = VIHC = VIHS = EVDD,
IDDH
In halt mode,
VIL = 0 V, no load,
fclk = 100 MHz,
TA = 25°C]
PLL multiple rate x 10,
division rate 1/1
35^{Note 1}
70^{Note 2}
mA
20^{Note 3}
mA
IDDS
In stop mode^{Note 4}, µPD77210
240
µA
fclk = 0 Hz,
µPD77213
120
PLL stop
Notes 1. The value is when MAC with Dual Load instruction 50% + nop instruction 50% are executed. It is
roughly estimated at 0.35 mA/MHz.
2. The value is when a special program that brings about frequent switching inside the device is
executed.
It is roughly estimated at 0.7 mA/MHz.
3. The value is when the division rate is 1/1. It is roughly estimated at 0.2 mA/MHz + IDDS using the
divided clock.
4. The value in stop mode is the value when PLL is stopped.
Data Sheet U15203EJ3V0DS
47