PD77210_15 Datasheet, PDF (51/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
AC Characteristics (TA = − 20 to + 70°C, with IVDD and EVDD within recommended operating condition range)
Clock
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
CLKIN cycle time^{Note 1}
tcCX
62.5
ns
CLKIN high level width
twCXH
12.5
ns
CLKIN low level width
twCXL
12.5
ns
CLKIN rise/fall time
trfCX
5
ns
Internal clock cycle time
tcC
Over 120 MHz(µPD77210
6.25
ns
only)
requirements
Under 120 MHz
8.33
ns
PLL lock-up time
tLPLL
PLL lock frequency ^{Note 1}
tcPLL
When boot:P3 = 0 ^{Note 2}
120
300
µs
160
MHz
When boot:P3 = 1
80
120
MHz
Notes 1. The CLKIN cycle time must accord with the PLL lock frequency. It is therefore necessary to satisfy both
the CLKIN cycle time condition of 62.5 ns (MIN.) and the PLL lock frequency condition of a multiplied
frequency in the range of 80 to 160 MHz.
2. In the µPD77213, it can be set only when an external memory boot is being used.
Switching characteristics
Parameter
Internal clock cycle^Note
CLKOUT cycle time
CLKOUT width
Symbol
tcC
tcCO
twCO
n=1
n≥2
Condition
High level width
Low level width
CLKOUT rise/fall time
trfCO
CLKOUT delay time
tdCO
Note m: Multiple ratio, n: Division ratio (PLL, divider)
MIN.
TYP.
MAX.
Unit
tcCX ÷ m × n
ns
tcC
ns
tcC ÷ 2
ns
tcC ÷ n
ns
tcC −
ns
tcC ÷ n
5
ns
6.25
ns
Data Sheet U15203EJ3V0DS
49