PD77210_15 Datasheet, PDF (25/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
2. FUNCTIONAL OUTLINE
2.1 Program Control Unit
This unit controls the execution of µPD77210 Family by executing instructions and controlling branching, loop,
interrupts, clock, and standby mode.
2.1.1 CPU control
A three-stage pipeline architecture is employed so that all instructions, except branch instructions and some
others, can be executed with one system clock.
2.1.2 Interrupt control
The interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin
(INTmn) or internal peripherals (such as the serial interface, host interface, timer, and DMA controller). The interrupt
of each interrupt source can be individually enabled or disabled. In addition, multiple interrupts are also supported.
2.1.3 Loop control stack
A loop function without any hardware overhead is realized. A 4-level loop stack is provided to support multiple
loops.
2.1.4 PC stack
A 15-level PC stack that stacks the program counter supports multiple interrupts/subroutine calls.
2.1.5 Clock control
A PLL and a divider are internally provided as a clock generator so that an externally input clock is multiplied or
divided and supplied as the operating clock to the µPD77210 Family. The multiple of the PLL can be set by using
external pins (PLL0 to PLL3) within a range of ×10 to 64. The division ratio can be set by using a register in a range
of ÷1 to 16.
The clock control register (CLKC) controls the power (ON/OFF) to the PLL, selects a clock source, controls the
output divider, and controls the output of the CLKOUT pin.
Two types of standby modes are available so that the power consumption can be reduced when the µPD77210
Family is standing by.
•HALT mode: Current consumption falls to several mA upon execution of the HALT instruction.
This mode is released by an interrupt or hardware reset.
•STOP mode: Current consumption falls to hundreds of µA^Note upon execution of the STOP instruction.
This mode is released by hardware reset or inputting a signal to CSTOP pin.
Note When the PLL is stopped
Data Sheet U15203EJ3V0DS
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