PD77210_15 Datasheet, PDF (18/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
• External data memory interface
Pin Name
Pin No.
I/O
Function
144-pin LQFP 161-pin FBGA
MA0 to
MA19^Note
84, 85,
90 to 97,
M6,N6,N7,P8,
M7,M8,P9,N8,
Output Address bus of external data memory
(3S) These pins output an address when the external data
100 to 107,
L8,N9,M9,N10,
memory is accessed.
111, 112
M10,P11,L10,
M11,N11,N12,
M13,M12
MD0 to
119,120,
J12,H13,G13,
I/O 16-bit data bus
MD15
125 to 132,
H14,H12,H11,
(3S) These pins input/output data when the external data
135 to 140
G14,F13,G12,
memory is accessed.
E13,F11,E14,
D13,F12,E12,
D14
MWR
116
K12
Output Write output
(3S) This pin outputs a write strobe signal for the external
data memory.
MRD
115
L13
Output Read output
(3S) This pin outputs a read strobe signal for the external
data memory.
MHOLDAK 114
L14
Output Hold acknowledge signal
This pin goes low when the external device is
granted use of the external data memory bus of the
µPD77210 Family.
MHOLDRQ 113
L12
Input Hold request signal
The external device inputs a low level to this pin
when it uses the external data memory bus of the
µPD77210 Family.
MWAIT
117
K13
Input Wait signal input
This pin inserts wait cycles when the µPD77210
Family accesses the external data memory.
• 0: Inserts wait cycles.
• 1: Does not insert wait cycles.
MBSTB
118
J13
Output Bus strobe signal
This pin goes low while the µPD77210 Family uses
the external data memory bus.
Note MA13 to MA19 pins of the µPD77213 are alternate function pins.
Alternate
Pin
SDCLK,
SDCR,
SDDAT0,
SDMON
−
−
−
−
−
−
−
Remark Those pins marked “3S” in the above table enter the high-impedance state under the following
conditions:
MA0 to MA19, MRD, and MWR: When the bus is released (MHOLDAK = low level)
MD0 to MD15: When the external data memory is not accessed and when the bus is released
(MHOLDAK = low level)
16
Data Sheet U15203EJ3V0DS