PD77210_15 Datasheet, PDF (34/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
7. MEMORY MAP
The µPD77210 Family employs a Harvard architecture that separates the instruction memory space from the data
memory space.
7.1 Instruction Memory
7.1.1 Instruction memory map
The instruction memory space consists of 64 Kwords × 32 bits. The area at addresses 0x8000 to 0xFFFF is a
paging area that supports a memory space of 64 Kwords or more by specifying a page by using the instruction
paging register (IPR).
The instruction ROM of the µPD77213 exists in the paging area and is accessed as IPR=0x0 or 0x1.
The paging area of the µPD77210 is reserved for future expansion.
0xFFFF
µ PD77210
0xFFFF
µ PD77213
Paging area
Paging area
(32 Kwords)
Paging area
(32 Kwords)
Instruction ROM^Note
(32 Kwords)
0x8000
0x7FFF
0x8000
0x7FFF
(IPR=0x0)
(IPR=0x1)
System area
Instruction RAM
(31.5 Kwords)
0x4000
0x3FFF
0x0200
0x01FF
0x0000
Boot-up ROM
(512 words)
Instruction RAM
(15.5 Kwords)
0x0200
0x01FF
0x0000
Boot-up ROM
(512 words)
Note The higher 8 words of the instruction ROM (0xFFF8 to 0xFFFF) constitute system area.
Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If
these addresses are accessed, correct operation of the device is not guaranteed.
A paging area in which no IPR page exists cannot be accessed. If this kind of paging area is
accessed, correct operation of the device is not guaranteed.
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Data Sheet U15203EJ3V0DS