PD77210_15 Datasheet, PDF (26/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
2.1.6 Instruction memory
Of the instruction RAM, 64 words are allocated as interrupt vectors.
The µPD77210 is provided with an instruction RAM of 31.5 Kwords. The µPD77213 is provided with an instruction
RAM of 15.5 Kwords and instruction ROM of 64 Kwords.
A boot-up ROM that boots up the instruction RAM is also provided, and the instruction RAM can be initialized or
rewritten by means of a memory boot (booting from an internal or external data space), host boot (booting via a host
interface), or serial boot (booting via a serial interface).
2.2 Operation Unit
This unit performs multiplication, addition, logic, and shift operations, and consists of a 40-bit multiply
accumulator, a 40-bit data ALU, a 40-bit barrel shifter, and eight 40-bit general-purpose registers.
2.2.1 General-purpose registers (R0 to R7)
These eight 40-bit registers input/output operands and load/store data to/from data memory.
Each register consists of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to 16), and R0E to R7E (bits
39 to 32). Depending on the type of the operation, RnL, RnH, and RnE are used either as one register or in
combination.
2.2.2 Multiply accumulator (MAC)
The multiply accumulator performs multiplication of two 16-bit data items and addition or subtraction between the
result of the multiplication and one 40-bit data item, and then outputs 40-bit data.
A shifter (MSFT: MAC shifter) is provided at the preceding stage of the MAC, so that the 40-bit data that is to be
added to or subtracted from the multiplication result can be arithmetically shifted 1 bit or 16 bits to the right before
addition or subtraction.
2.2.3 Arithmetic logic unit (ALU)
The ALU accepts one or two 40-bit data items as input, performs an arithmetic or logical operation, and then
outputs 40-bit data.
2.2.4 Barrel shifter (BSFT)
The BFST accepts 40-bit data items as input, shifts the data to the left or right by an arbitrary number of bits, and
then outputs 40-bit data. The data can be shifted to the right arithmetically, in which case the sign of the data is
extended, or logically in which case 0 is inserted starting from the MSB.
2.3 Data Memory Unit
The data memory unit consists of two planes of data memory spaces and two pairs of data addressing units.
2.3.1 Data memory
Two data memory planes (X data memory and Y data memory) are provided. The data memory space includes a
64-word peripheral area.
The µPD77210 has a data RAM consisting of 30 Kwords × 2 planes. The µPD77213 has a data RAM consisting
of 18 Kwords × 2 planes, and has a data ROM consisting of 32 Kwords × 2 planes.
In addition, They also have an external data memory interface that is used to connect an external 1 Mword data
memory to the device.
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Data Sheet U15203EJ3V0DS