PD77210_15 Datasheet, PDF (37/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
7.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
Cautions
1. The register names shown in the above table are not reserved words in either assembler or
C. To use these names in assembler or C, therefore, the user must define them.
2. The same register is accessed regardless of whether the X memory space or Y memory
space is accessed, provided that the address is the same.
3. Different registers cannot be accessed simultaneously from the X and Y memory spaces.
X/Y Memory Address
Memory-Mapped Peripherals (1/3)
Register Name
Function
0x3800
0x3801
0x3802
0x3803
0x3804
0x3805
0x3806
0x3807
0x3808 to 0x380F
0x3810
0x3811
0x3812
0x3813 to 0x381F
0x3820
0x3821
0x3822 to 0x383F
0x3840
0x3841
0x3842
0x3843
0x3844
0x3845
0x3846
0x3847
0x3848
0x3849
0x384A
0x384B
0x384C
0x384D to 0x384F
0x3850
0x3851
0x3852
0x3853
TSDT/SDT1
SST1
TSST
TFMT
TTXL
TTXH
TRXL
TRXH
Reserved area
ASDT/SDT2
SST2
ASST
Reserved area
HDT
HST
Reserved area
MDT
MSHW
MCST
MWAIT
MIDX
MADRLI
MADRHI
MOFSI
MLENI
MADRLO
MADRHO
MOFSO
MLENO
Reserved area
PMSA0
PMS0
PMC0
PMP0
TDM serial data register/Serial data register 1
Serial status register 1
TDM serial status register
TDM frame format register
TDM transfer slot register (low)
TDM transfer slot register (high)
TDM receive slot register (low)
TDM receive slot register (high)
Caution Do not access this area.
Audio serial data register/Serial data register 2
Serial status register 2
Audio serial status register
Caution Do not access this area.
Host interface data register
Host interface status register
Caution Do not access this area.
Memory data register
Memory I/F setup/hold width setting register
Memory I/F control/status register
Memory I/F wait register
Direct access index register
Memory I/F input start address register (low)
Memory I/F input start address register (high)
Memory I/F input line offset register
Memory I/F input line length register
Memory I/F output start address register (low)
Memory I/F output start address register (high)
Memory I/F output line offset register
Memory I/F output line length register
Caution Do not access this area.
PMT start address register 0
PMT size register 0
PMT control register 0
PMT address pointer 0
Peripheral
Name
TSIO(SIO1)
−
ASIO(SIO2)
−
HIO
−
MIO
−
PMT ch0
Data Sheet U15203EJ3V0DS
35