PD77210_15 Datasheet, PDF (28/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
2.4.3 General-purpose I/O port (PIO)
This is a 16-bit I/O port that can be set to either input or output mode in 1-bit units.
The external pins alternate between interrupt pins and host interface pins. By setting the mode of 8 bits of the
port to host interface pin mode, the host interface can be set in the 16-bit parallel mode.
2.4.4 External memory interface (MIO)
This interface accesses an external 1 Mwords data memory area in either of two modes: direct access and DMA
access modes. In DMA access mode, access is made via a memory-mapped register.
In direct access mode, the data paging register (DPR) is set to 0x3F and a page area is accessed as an access
window. An address of the external memory consists of 20 bits with the 8-bit value of the index register added as bits
12 to 19.
In DMA access mode, the address is automatically updated when a memory-mapped register is accessed. The
address is updated in an increment addressing mode in which the address is simply incremented, or in two-
dimensional addressing mode in which an offset is added to each line length.
The number of wait cycles to be inserted when the external memory is accessed can be specified by a register
(MWAIT), within a range of 1 to 15. In addition, wait cycles can also be inserted by using the MWAIT pin.
2.4.5 Timers (TIM1 and TIM2)
The µPD77210 Family has two timer channels.
These timers can be used as interval timers, event counters, watchdog timers, and free-run timers.
The clock input to the timers is selected from the system clock, serial clock (ASCK or TSCK), external interrupt
(INT00, INT10, INT20, or INT30), or output of each timer.
The count value is 16 bits and the clock input by the prescaler can be divided by 1, 2, 4, 8, 16, 32, 64, or 128.
2.4.6 Interrupt controller (INTC)
The interrupt controller has functions for selecting and masking interrupt signals. It controls the interrupt signal to
be input to the DSP core.
2.4.7 DMA controller (PMT)
The DMA controller realizes data transfer between the peripherals and memory (peripheral-memory transfer) in
the background. It mitigates the software overhead generated by interrupt processing of the data input/output via
SIO, HIO, MIO, and SDCIF (µPD77213 only).
Data of 14 Kwords at addresses 0x0000 to 0x37FF of the internal data RAM can be transferred by means of
DMA.
2.4.8 SD card interface (SDCIF)
The µPD77213 supports SD Card interface. This interface is for access of SD card. It supports the DMA transfer
for input data to internal data RAM. The SD card is accessed by using a dedicated routine of system ROM.
2.4.9 Debug interface (IEIO)
The µPD77210 Family has the following functions that conform to the JTAG (Joint Test Action Group) interface as
a debug interface.
A device conforming to JTAG has an access port dedicated to testing and can be tested independently of the
internal logic.
The µPD77210 Family has registers and a control circuit for in-circuit emulation, in addition to the instruction
registers, bypass registers, and boundary scan registers that are required by the JTAG Recommendation.
26
Data Sheet U15203EJ3V0DS