PD77210_15 Datasheet, PDF (16/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
• Clock and system control pins
Pin Name
Pin No.
144-pin LQFP 161-pin FBGA
CLKIN
20
C6
CLKOUT 25
B6
PLL0 to
PLL3
14 to 17
A9,B9,C7,B8
HALTS
13
C8
STOPS
11
A10
CSTOP
12
B10
I/O
Function
Input
Output
Input
Output
Output
Input
Clock input
This pin inputs a clock to operate the µPD77210
Family.
Internal system clock output
This pin outputs the internal system clock that is the
clock input from CLKIN and which is multiplied by the
PLL circuit.
PLL multiple setting input
These pins set a clock multiple of the PLL circuit.
• PLL3: PLL2: PLL1: PLL0
0000: x10
0001: x12
0010: x14
0011: x16
0100: x18
0101: x20
0110: x22
0111: x24
1000: x26
1001: x28
1010: x30
1011: x32
1100: x40
1101: x48
1110: x56
1111: x64
HALT mode status output
This pin is asserted active in halt mode and stop
mode.
Stop mode status output
This pin is asserted active in stop mode.
Stop mode clear signal input
Stop mode is cleared when this pin is asserted
active.
Alternate
Pin
−
−
−
−
−
−
14
Data Sheet U15203EJ3V0DS