PD77210_15 Datasheet, PDF (27/76 Pages) Renesas Technology Corp – 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

µPD77210, 77213
2.3.2 Data addressing unit
An independent data addressing unit is provided for each of the X and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one module register (DMX or
DMY), and an address ALU.
2.4 Peripheral Unit
The peripheral unit has serial interfaces, a host interface, general-purpose I/O ports, timers, an external memory
interface, and SD card interface (µPD77213 only). All these internal peripherals are mapped to the X and Y data
memory spaces and are accessed as memory-mapped I/Os by the program.
2.4.1 Serial interface (SIO)
Two serial interface channels, an audio serial interface (ASIO) and a time-division serial interface (TDMSIO), are
provided.
The audio serial interface can be used in either of two modes: audio mode and standard mode. The standard
mode is compatible with the existing µPD77111 Family. The audio mode is compatible with the µPD77115.
The features of the audio mode are as follows:
• Mode: Master mode and slave mode
Master mode: Supports master clock input (MCLK), bit clock output (BCLK), LR clock output (LRCLK), 256 fs,
384 fs, and 512 fs.
Slave mode: Bit clock input (BCLK) and LR clock input (LRCLK)
• Frame format: 32- or 64-bit audio formats (LRCLK format)
• Handshake: Handshaking with external devices by a dedicated frame signal (LRCLK) and with the internal
circuitry by polling, wait, or interrupt
The standard mode has the following features:
•Serial clock:
•Frame length:
•Handshake:
Supplied from an external source to each channel. The clock is shared for input and output by
each channel.
8 or 16 bits, with MSB or LSB first selected for each channel.
Handshaking with the external device by using a dedicated status signal and with the internal
circuitry by polling, wait, or interrupt.
The time-division serial interface divides the serial input/output signal into 1 to 32 time slots and allows several
devices to share the serial bus. Because the T1 and E1 frame signals are considered. The time slot can be extended
from 1 to 128.
2.4.2 Host interface (HIO)
This is a parallel port that inputs/outputs data from/to an external host CPU and DMA controller. It can be used in
either 8-bit parallel mode or 16-bit parallel mode. In the µPD77210 Family, 16-bit registers are mapped to memory
for input data, output data, and status. Handshaking with an external device is performed by using a dedicated
status signal, and the internal circuitry handshaking is done by means of polling, wait, or interrupts.
The 8-bit parallel mode is compatible with the existing members of the µPD77111 Family.
In 16-bit parallel mode, some port pins are used as host interface pins.
Data Sheet U15203EJ3V0DS
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