RX630_15 Datasheet, PDF (136/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
5. Electrical Characteristics
5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Table 5.27 Power-on Reset Circuit and Voltage Detection Circuit Characteristics
Conditions: VCC = AVCC0 = VREFH = VCC_USB = V_BATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
T_a = T_opr
Item
Symbol
Min.
Typ.
Max.
Unit Test Conditions
Voltage detection Power-on reset
level
(POR)
Low power
consumption
function disabled
V_POR
2.5
2.6
2.7
V
Figure 5.40
Low power
consumption
function enabled
2.0
2.35
2.7
Voltage detection circuit (LVD0)
Voltage detection circuit (LVD1)
Voltage detection circuit (LVD2)
Internal reset time Power-on reset time
LVD0 reset time
LVD1 reset time
LVD2 reset time
Minimum VCC down time
V_det0
V_{det1_A}
V_{det2_A}
t_POR
t_LVD0
t_LVD1
t_LVD2
t_VOFF
2.7
2.80
2.9
Figure 5.41
2.75
2.95
3.15
2.75
2.95
3.15
—
4.6
—
ms Figure 5.40
—
4.6
—
Figure 5.41
—
0.9
—
Figure 5.42
—
0.9
—
Figure 5.43
200
—
—
µs Figure 5.40 and
Figure 5.41
Response delay time
t_det
—
—
200
µs Figure 5.40 to
Figure 5.43
LVD operation stabilization time (after LVD is enabled)
Td_(E-A)
—
—
3
µs Figure 5.42 and
Hysteresis width (LVD1 and LVD2)
V _LVH
—
80
—
mV ^{Figure 5.43}
Note: The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels V_POR, V_det1,
and V_det2 for the POR/ LVD.
t_VOFF
VCC
V_POR
Internal reset signal
(active-low)
Figure 5.40 Power-on Reset Timing
t_det t_POR
t_det t_det t_POR
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 136 of 154