RX630_15 Datasheet, PDF (122/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
5. Electrical Characteristics
5.3.6
Timing of On-Chip Peripheral Modules
Table 5.16 Timing of On-Chip Peripheral Modules (1)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Symbol Min.
I/O ports Input data pulse width
t_PRW
1.5
MTU/TPU Input capture input pulse
Single-edge
t_TICW
1.5
width
setting
Both-edge
2.5
setting
Timer clock pulse width
Single-edge
setting
Both-edge
setting
t_TCKWH,
1.5
t_TCKWL
2.5
Phase counting
2.5
mode
POE
POE# input pulse width
8-bit timer Timer clock pulse width
Single-edge
setting
Both-edge
setting
t_POEW
1.5
t_TMCWH,
1.5
t_TMCWL
2.5
SCI
Input clock cycle
Asynchronous t_Scyc
4
Clock
6
synchronous
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
t_SCKW
0.4
t_SCKr
—
t_SCKf
—
Asynchronous t_Scyc
16
Clock
4
synchronous
Output clock pulse width
Output clock rise time
Output clock fall time
Transmit data delay time
t_SCKW
0.4
t_SCKr
—
t_SCKf
—
Clock
t_TXD
—
synchronous
Receive data setup time
Clock
t_RXS
40
synchronous
Receive data hold time
Clock
t_RXH
40
synchronous
A/D
10-bit A/D converter trigger input pulse width
t_TRGW
1.5
converter _{12-bit A/D converter trigger input pulse width}
1.5
Note 1. t_Pcyc: PCLK cycle
Max.
—
—
—
—
—
—
—
—
—
—
—
0.6
20
20
—
—
0.6
20
20
40
—
—
—
—
Unit*¹
t_Pcyc
t_Pcyc
Test
Conditions
Figure 5.24
Figure 5.25
t_Pcyc
Figure 5.26
t_Pcyc
t_Pcyc
Figure 5.27
Figure 5.28
t_Pcyc
Figure 5.29
t_Scyc
ns
ns
t_Pcyc
t_Scyc
ns
ns
ns
ns
ns
t_Pcyc
Figure 5.30
Figure 5.31
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 122 of 154