RX630_15 Datasheet, PDF(110/156 Page) Renesas Technology Corp

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RX630_15 Datasheet, PDF (110/156 Pages) Renesas Technology Corp – Renesas MCUs

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RX630 Group

5. Electrical Characteristics

5.3.2

Clock Timing

Table 5.11 Clock Timing (Except for Sub-Clock Related)

Conditions: VCC = AVCC0 = VREFH = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0,

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr

Item

Symbol

Min.

Typ.

BCLK pin output cycle time

tBcyc

BCLK pin output high pulse width

tCH

BCLK pin output low pulse width

tCL

BCLK pin output rising time

tCr

BCLK pin output falling time

tCf

EXTAL external clock input cycle time

tEXcyc

EXTAL external clock input high pulse width

tEXH

EXTAL external clock input low pulse width

tEXL

EXTAL external clock rising time

tEXr

EXTAL external clock falling time

tEXf

EXTAL external clock input wait time*1

tEXWT

Main clock oscillator oscillation frequency

fMAIN

Main clock oscillation stabilization time (crystal)

tMAINOSC

Main clock oscillation stabilization wait time (crystal)

tMAINOSCWT â

LOCO and IWDTCLK clock cycle time

tcyc

6.96

LOCO and IWDTCLK clock oscillation frequency

fLOCO

106.25 125

LOCO and IWDTCLK clock oscillation stabilization wait time

tLOCOWT

HOCO clock oscillator oscillation frequency

fHOCO

HOCO clock oscillation stabilization wait time 1*2

tHOCOWT1

HOCO clock oscillation stabilization wait time 2

tHOCOWT2

HOCO clock power supply settling time

tHOCOP

PLL circuit oscillation frequency

fPLL

104

PLL clock oscillation stabilization time PLL operation started tPLL1

after main clock

PLL clock oscillation stabilization wait oscillation has settled tPLLWT1

PLL clock oscillation stabilization time PLL operation started tPLL2

before main clock

oscillation has settled

PLL clock oscillation stabilization wait

tPLLWT2

Max. Unit

MHz

â*3

â*4

9.4

Âµs

143.75 kHz

Âµs

MHz

1.8

2.0

200

MHz

500

Âµs

â*5

tMAINOSC

+tPLL1

â*5

Test

Conditions

Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 5.7

Figure 5.8

Figure 5.9

Figure 5.10

Figure 5.11

Note 1.

Note 2.

Note 3.

Note 4.

This is the time until the clock is used after setting P36 and P37 as inputs, and then clearing the main clock oscillator stop bit

(MOSCCR.MOSTP) to 0 (selecting operation).

This is the time until the frequency of oscillation by the HOCO (fHOCO) reaches the range for guaranteed operation. after

release from the reset state.

When using a main clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

The number of cycles n selected by the value of the MOSCWTCR.MSTS[4:0] bits determines the main-clock oscillation

stabilization waiting time in accord with the formula below.

n +16384

tMAINOSCWT = tMAINOSC +

fMAIN

Note 5. The number of cycles n selected by the value of the PLLWTCR.PSTS[4:0] bits determines the PLL-clock oscillation stabilization

waiting time in accord with the formula below.

n +131072

tPLLWT1 = tPLL1 +

fPLL

n +131072

tPLLWT2 = tPLL2 +

fPLL

= tMAINOSC + tPLL1 +

fPLL

R01DS0060EJ0160 Rev.1.60

May 19, 2014

Page 110 of 154

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