RX630_15 Datasheet, PDF (125/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
5. Electrical Characteristics
Table 5.19 Timing of On-Chip Peripheral Modules (4)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
Symb
ol
Min.*^1,*²
Max.
Unit
Test
Conditions
RIIC
(Standard-mode,
SMBus)
ICFER.FMPE = 0
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
t_SCL 6(12) × t_IICcyc + 1300 —
t_SCLH 3(6) × t_IICcyc + 300
—
t_SCLL 3(6) × t_IICcyc + 300
—
ns Figure 5.37
ns
ns
SCL, SDA input rise time
t_Sr
—
1000
ns
SCL, SDA input fall time
t_Sf
—
300
ns
SCL, SDA input spike pulse removal time t_SP
0
1(4) × t_IICcyc ns
SDA input bus free time
t_BUF 3(6) × t_IICcyc + 300
—
ns
Start condition input hold time
t_STAH t_IICcyc + 300
—
ns
Restart condition input setup time
t_STAS 1000
—
ns
Stop condition input setup time
t_STOS 1000
—
ns
Data input setup time
t_SDAS t_IICcyc + 50
—
ns
Data input hold time
t_SDAH 0
—
ns
SCL, SDA capacitive load
C_b
—
400
pF
RIIC
(Fast-mode)
SCL input cycle time
SCL input high pulse width
t_SCL 6(12) × t_IICcyc + 600
—
ns
t_SCLH 3(6) × t_IICcyc + 300
—
ns
SCL input low pulse width
t_SCLL 3(6) × t_IICcyc + 300
—
ns
SCL, SDA input rise time
t_Sr
20 + 0.1C_b
300
ns
SCL, SDA input fall time
t_Sf
20 + 0.1C_b
300
ns
SCL, SDA input spike pulse removal time t_SP
0
1(4) × t_IICcyc ns
SDA input bus free time
t_BUF 3(6) × t_IICcyc + 300
—
ns
Start condition input hold time
t_STAH t_IICcyc + 300
—
ns
Restart condition input setup time
t_STAS 300
—
ns
Stop condition input setup time
t_STOS 300
—
ns
Data input setup time
t_SDAS t_IICcyc + 50
—
ns
Data input hold time
t_SDAH 0
—
ns
SCL, SDA capacitive load
C_b
—
400
pF
Note:
Note 1.
Note 2.
t_IICcyc: RIIC internal reference clock (IIC) Cycle
The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by
the setting ICFER.NFE = 1.
Cb is the total capacitance of the bus lines.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 125 of 154