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RX630_15 Datasheet, PDF (126/156 Pages) Renesas Technology Corp – Renesas MCUs
RX630 Group
5. Electrical Characteristics
Table 5.20 Timing of On-Chip Peripheral Modules (5)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V
PCLK = 8 to 50 MHz
Ta = Topr
High drive output is selected by the drive capacity control register.
Item
Symbol Min.*, *2
Max.*
Unit
Test
Conditions
RIIC
(Fast-mode+)
ICFER.FMPE = 1
Simple IIC
(Standard-mode)
Simple IIC
(Fast-mode)
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
SDA input bus free time
Start condition input hold time
Restart condition input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SDA input rise time
SDA input fall time
SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse removal time
Data input setup time
Data input hold time
SCL, SDA capacitive load
tSCL
tSCLH
tSCLL
tSr
tSf
tSP
tBUF
tSTAH
tSTAS
tSTOS
tSDAS
tSDAH
Cb
tSr
tSf
tSP
tSDAS
tSDAH
Cb
tSr
tSf
tSP
tSDAS
tSDAH
Cb
6(12) × tIICcyc + 240
3(6) × tIICcyc + 120
3(6) × tIICcyc + 120
—
—
0
3(6) × tIICcyc + 120
tIICcyc + 120
120
120
tIICcyc + 120
0
—
—
—
0
250
0
—
20 + 0.1Cb
20 + 0.1Cb
0
100
0
—
—
ns Figure
—
ns 5.37
—
ns
120
ns
120
ns
1(4) × tIICcyc ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
550
pF
1000
ns
300
ns
4 × tIICcyc
ns
—
ns
—
ns
400
pF
300
ns
300
ns
4 × tIICcyc
ns
—
ns
—
ns
400
pF
Note: tIICcyc: RIIC internal reference clock (IIC) Cycle, tPcyc: PCLK cycle
Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1.
Note 2. Cb indicates the total capacity of the bus line.
PCLK
Port
tPRW
Figure 5.24 I/O Port Input Timing
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 126 of 154