RX630_15 Datasheet, PDF (123/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
5. Electrical Characteristics
Table 5.17 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V*¹, VREFH0 = 3.0 V to AVCC0*¹,
VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V,
PCLK = 8 to 50 MHz,
T_a = T_opr
High drive output is selected by the drive capacity control register.
Item
RSPI RSPCK clock cycle
RSPCK clock high pulse
width
RSPCK clock low pulse
width
RSPCK clock rise/fall time
Data input setup time
Data input hold time
SSL setup time
SSL hold time
Data output delay time
Data output hold time
Successive transmission
delay time
MOSI and MISO rise/
fall time
SSL rise/fall time
Slave access time
Slave output release time
Master
Slave
Master
Slave
Master
Slave
Output
Input
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Output
Input
Output
Input
Symbol Min.
t_SPcyc
2
8
t_SPCKWH
t_SPCKWL
t_SPCKr,
t_SPCKf
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2 – 3
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2 – 3
(t_SPcyc – t_SPCKR
– t_SPCKF) / 2
—
—
VCC  3.0 V t_SU
15
VCC < 3.0 V
20
t_H
t_LEAD
20 – t_Pcyc
0
20 + 2 × t_Pcyc
1
4
t_LAG
1
4
t_OD
—
—
t_OH
0
0
t_TD
t_SPcyc + 2 × t_Pcyc
t_Dr, t_Df
t_SSLr,
t_SSLf
t_SA
t_REL
4 × t_Pcyc
—
—
—
—
—
—
Max.
4096
4096
—
Unit*²
t_Pcyc
ns
—
—
ns
—
5
ns
1
μs
—
ns
—
—
—
ns
—
8
t_SPcyc
—
t_Pcyc
8
t_SPcyc
—
t_Pcyc
18
ns
3 × t_Pcyc + 40
—
ns
—
8 × t_SPcyc
ns
+ 2 × t_Pcyc
—
5
ns
1
μs
5
ns
1
μs
4
t_Pcyc
3
t_Pcyc
Test Conditions
C = 30_PF,
Figure 5.32
C = 30_PF,
Figure 5.33 to
Figure 5.36
C = 30_PF,
Figure 5.35 and
Figure 5.36
Note 1. When operation at 3.0 V or a lower voltage is needed, please contact a Renesas sales office.
Note 2. t_Pcyc: PCLK cycle
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 123 of 154