RX630_15 Datasheet, PDF(111/156 Page) Renesas Technology Corp

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RX630_15 Datasheet, PDF (111/156 Pages) Renesas Technology Corp – Renesas MCUs

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RX630 Group

5. Electrical Characteristics

Table 5.12 Clock Timing (Sub-Clock Related)

Conditions: VCC = AVCC0 = VREFH = VCC_USB = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, VBATT = 2.3 to 3.6 V,

VSS = AVSS0 = VREFL/VREFL0 = VSS_USB = 0 V, Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Sub-clock oscillator oscillation frequency

Sub-clock oscillation stabilization time

Sub-clock oscillation stabilization wait offset time*2

Sub-clock oscillation stabilization waiting time

fSUB

32.768

kHz

tSUBOSC

Figure 5.12

tSUBOSCWT0

1.8

2.6

tSUBOSCWT

Note 1. When using a sub-clock, ask the manufacturer of the oscillator to evaluate its oscillation. Refer to the results of evaluation

provided by the manufacturer for the oscillation stabilization time.

Note 2. The minimum and maximum values for sub-clock oscillation stabilization waiting offset time (tSUBOSCWT0) only apply to products

tagged with â*1â in Figure 1.3, List of Products. For other products, take the value of (tSUBOSCWT0) to be 0.

Note 3. The number of cycles n selected by the value of the SOSCWTCR.SSTS[4:0] bits determines the sub-clock oscillation

stabilization waiting time in accord with the formula below.

tSUBOSCWT = max (tSUBOSC, tSUBOSCWT0) + fSUB

The notation âmax(tSUBOSC, tSUBOSCWT0)â indicates whichever is higher of tSUBOSC and tSUBOSCWT0.

BCLK pin output

tBcyc

tCH

tCf

tCL

tCr

Test conditions: VOH = VCC Ã 0.7, VOL = VCC Ã 0.3, IOH = â1.0 mA, IOL = 1.0 mA, C = 30 pF

Figure 5.3 BCLK Pin Output Timing

tEXH

tEXcyc

tEXL

EXTAL external clock input

tEXr

tEXf

Figure 5.4 EXTAL External Clock Input Timing

VCC Ã 0.5

R01DS0060EJ0160 Rev.1.60

May 19, 2014

Page 111 of 154

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