RX630_15 Datasheet, PDF (11/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
1.3 Block Diagram
Figure 1.2 shows a block diagram.
1. Overview
ROM
RAM
RX CPU
MPU
Clock
generation
circuit
ICUb
DTCa
DMACA ×
4 channels
E2 DataFlash
WDTA
IWDTa
CRC
SCIc × 12 channels
SCId × 1 channel
USBa × 1 port
RSPI (unit 0)
RSPI (unit 1)
RSPI (unit 2)
CAN × 3 channels
MTU2a × 6 channels
POE2a
TPUa × 6 channels (unit 0)
TPUa × 6 channels (unit 1)
PPG (unit 0)
PPG (unit 1)
TMR × 2 channels (unit 0)
TMR × 2 channels (unit 1)
CMT × 2 channels (unit 0)
CMT × 2 channels (unit 1)
RTCa
RIIC × 4 channels
IEB
12-bit ADC × 21 channels
10-bit ADC × 8 channels
10-bit DAC × 2 channels
Temperature sensor
BSC
External bus
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
ICUb:
Interrupt controller
DTCa:
Data transfer controller
DMACA: DMA controller
BSC:
Bus controller
WDTA: Watchdog timer
IWDTa: Independent watchdog timer
CRC:
CRC (cyclic redundancy check) calculator
SCIc, SCId: Serial communications interface
USBa:
USB 2.0 function module
RSPI:
Serial peripheral interface
MPU:
Memory protection unit
CAN: CAN module
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
TPUa: 16-bit timer pulse unit
PPG: Programmable pulse generator
TMR: 8-bit timer
CMT: Compare match timer
RTCa: Realtime clock
RIIC: I²C bus interface
IEB: IEBus controller
Figure 1.2
Block Diagram
R01DS0060EJ0160 Rev.1.60
May 19, 2014
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