RX630_15 Datasheet, PDF (101/156 Pages) Renesas Technology Corp – Renesas MCUs

RX630 Group
4. I/O Registers
Table 4.1
Address
007F C402h
007F C410h
007F C411h
007F C412h
007F C440h
007F C442h
007F C450h
007F C452h
007F C454h
007F FFB0h
007F FFB1h
007F FFB2h
007F FFB4h
007F FFB6h
007F FFBAh
007F FFC8h
007F FFCAh
007F FFCCh
007F FFCEh
007F FFE8h
FEFF FAC0h
FEFF FAC1h
FEFF FAC2h
FEFF FAC3h
FEFF FAC4h
FEFF FAC5h
FEFF FAC6h
FEFF FAC7h
FEFF FAC8h
FEFF FAC9h
FEFF FACAh
FEFF FACBh
FEFF FACCh
FEFF FACDh
FEFF FACEh
FEFF FACFh
FEFF FAD2h
FEFF FAD3h
List of I/O Registers (Address Order) (42/42)
Module
Symbol
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
FLASH
TEMPS
TEMPS
Register Name
Flash mode register
Flash access status register
Flash access error interrupt enable register
Flash ready interrupt enable register
E2 DataFlash read enable register 0
E2 DataFlash read enable register 1
E2 DataFlash P/E enable register 0
E2 DataFlash P/E enable register 1
FCU RAM enable register
Flash status register 0
Flash status register 1
Flash P/E mode entry register
Flash protection register
Flash reset register
FCU command register
FCU processing switching register
E2 data flash blank check control register
Flash P/E status register
E2 DataFlash blank check status register
Peripheral clock notification register
Unique ID register 0*⁹
Unique ID register 1*⁹
Unique ID register 2*⁹
Unique ID register 3*⁹
Unique ID register 4*⁹
Unique ID register 5*⁹
Unique ID register 6*⁹
Unique ID register 7*⁹
Unique ID register 8*⁹
Unique ID register 9*⁹
Unique ID register 10*⁹
Unique ID register 11*⁹
Unique ID register 12*⁹
Unique ID register 13*⁹
Unique ID register 14*⁹
Unique ID register 15*⁹
Temperature sensor calibration data register*⁹
Temperature sensor calibration data register*⁹
Register
Symbol
FMODR
FASTAT
FAEINT
FRDYIE
DFLRE0
DFLRE1
DFLWE0
DFLWE1
FCURAME
FSTATR0
FSTATR1
FENTRYR
FPROTR
FRESETR
FCMDR
FCPSR
DFLBCCNT
FPESTAT
DFLBCSTAT
PCKAR
UIDR0
UIDR1
UIDR2
UIDR3
UIDR4
UIDR5
UIDR6
UIDR7
UIDR8
UIDR9
UIDR10
UIDR11
UIDR12
UIDR13
UIDR14
UIDR15
TSCDRL
TSCDRH
Number of Access States
Number Access
Related
of Bits Size
ICLK PCLK ICLK  PCLK Function
8
8
2, 3 FCLK
2, 3 ICLK Flash Memory
8
8
2, 3 FCLK
2, 3 ICLK
8
8
2, 3 FCLK
2, 3 ICLK
8
8
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
8
8
2, 3 FCLK
2, 3 ICLK
8
8
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
16
16
2, 3 FCLK
2, 3 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
1 ICLK
8
8
1 ICLK
8
8
1 ICLK
1 ICLK
1 ICLK
Temperature
sensor
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Note 8.
Note 9.
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address is 000881ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 000881EEh and 000881ECh, respectively.
When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address is 000881EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 000881EFh and 000881EDh, respectively.
When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address is 000881FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 000881FEh and 000881FCh, respectively.
When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Odd addresses should not be accessed in 16-bit units. When accessing a register in 16-bit units, access the address of the TMR0 or TMR2 register. Table 26.4 lists
register allocation for 16-bit access in the User’s manual: Hardware.
The CAN2 module is not provided in products less than 1 Mbyte of ROM.
The CAN0 module is not provided in products less than 512 Kbytes of ROM.
When the register is accessed while the USB is operating, a delay may be generated in accessing.
These registers are only present in the G version.
R01DS0060EJ0160 Rev.1.60
May 19, 2014
Page 101 of 154