HYB18M1G16 Datasheet, PDF (8/65 Pages) Qimonda AG – 1-Gbit x16 DDR Mobile-RAM

Data Sheet
1.4
Ball Definition and Description
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
TABLE 4
Ball Description
Ball
Type Detailed Function
CK, CK
Input
CKE or CKE0, Input
CKE1
CS0
Input
CS1
RAS, CAS, WE Input
DQ0 - DQ15 I/O
LDQS, UDQS I/O
LDM, UDM
Input
BA0, BA1
Input
A0 - A12
Input
V_DDQ
V_SSQ
V_DD
V_SS
N.C.
Supply
Supply
Supply
Supply
–
Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on
crossing of the positive edge of CK and negative edge of CK.
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides precharge power-down and self
refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be
maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE
are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Data Inputs/Output: Bi-directional data bus (16 bit)
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered
with write data. Used to capture write data.
LDQS corresponds to the data on DQ0 - DQ7, UDQS to the data on DQ8 - DQ15
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM balls are input only, the DM loading matches the DQ and DQS
loading. DM may be driven HIGH, LOW, or floating during READs. LDM corresponds to the data
on DQ0 - DQ7, UDM to the data on DQ8 - DQ15
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be
loaded during a MODE REGISTER SET command (MRS or EMRS).
Address Inputs: Provide the row address for ACTIVE commands and the column address and
Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array
in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether
the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is
to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-
code during a MODE REGISTER SET command.
I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: V_DDQ = 1.70
V − 1.90 V
I/O Ground
Power Supply: Power for the core logic and input buffers, V_DD = 1.70 V − 1.90 V
Ground
No Connect
Rev.1.0, 2007-03
8
10242006-Y557-TZXW